Friday, December 31, 2010

ZPUino Alpha 1 is out. And its website too.

I'm proud to announce the first ZPUino release (Alpha 1). This release is aimed at developers and not yet for general use. There is still a lot of documentation missing, as well as build instructions for all the components.

Also a new website is up for ZPUino at, where all information for this release can be found. You will find there also contact information to report bugs, post fixes and request features.

So, I wish you all a happy new year!


Monday, December 27, 2010

Preparing Alpha1

Currently preparing release Alpha 1 of ZPUino, hopefully before end of year.

This first alpha will only support Linux, because I still have to port the programmer to windows platform. MacOS users should have no trouble building programmer from scratch.


Saturday, December 4, 2010

ADC from Gadget Factory

I finally had some time to solder the SPI ADC from Gadget Factory and give it a try on ZPUino and Papilio One.

Works :)

Values seem very consistent, so I'll try to adapt my oscope to this new ADC.


Friday, December 3, 2010

Papilio One

Things are coming out smooth :) After some bug-fixing on software side, and some new improvements, ZPUino runs on Papilio One FPGA (S3E-250), and is able to program sketches and even program itself. And programming is quite faster than "traditional" JTAG-based programmer (think 300+ seconds versus 20 seconds to program FPGA bitstream). The Arduino "ASCII" example runs perfectly now. I'll try to get all other examples working soon. Serial buffer was increased to 2Kb, and programming now uses 1Mbps instead of 115200. Some new routines were added to bootloader to allow fast programming of SST flash devices.

Another feature is soft reset using the serial line. So you can reset ZPUino even when it is in a very bad state, just by sending a "serial break", of a special serial code using 300 baud rate. Very useful for programming (no need to hand-reset), and when you use some serial terminal (just send a break and it will happily reset).


Friday, November 12, 2010

Some updates, new boards

Some updates were pushed, most regarding the new Papilio One Board I received today (Jack: thanks again for the prototypes).

Simulator should also work now perfectly, I found some issues with endianness which are already fixed.

The Arduino IDE is also now able to program the simulator directly from IDE. It's very nice.

I'll focus on new boards from Gadget Factory, the Papilio One and the Papilio Uno :) Pretty confusing, but one is a standalone board and other is meant to be used as an Arduino Shield.

So far ZPUino uses 60% of low-end Papilio boards - this does not mean that it can only grow 40% more, means that after 100% we might need to slow down speed to use otherwise unused resources (ask me for clarification if you never heard of related logic packing).


Sunday, October 24, 2010

Social Networks Update

You can now find ZPUino in Twitter and Facebook.

Enjoy the news updates! :)

Also a new web page is on the forge, I hope to upload it soon.


Saturday, October 23, 2010

UI for ZPUino

Just forked Arduino UI and added specifics for ZPUino. Should work to some extent (some changes still required due to PPS).

You can get it here:


Tuesday, October 19, 2010

PPS implemented

PPS is now implemented and tested. I uploaded to main git repository.

It can be disabled if one wishes, because it uses more LUTs than CPU core. Bootloader is now tuned to S3E eval board, new boards should arrive soon.

GPIO width was increased to maximum of 128 GPIO pins. Unused pins will be removed during synthesis.

Also I changed bootloader from C code to C++ code. This allows for template-based inlined functions for pinMode and digitalWrite, as well as other goodies that C++ can bring.


Saturday, October 16, 2010

New features, GUI first version

A new "interesting" feature is now under development, which is PPS - Peripheral Pin Select. This feature (although a LUT eater) allows you to redirect any peripheral pin (such as UART tx/rx, SPI) to any GPIO you might wish - and you can do it in run-time. Some microchip PIC include this feature, and for boards who do not actually include external devices it's always nice to be able to plug them in any connector board might provide, and redirect things like UART and SPI there.

Changes to Arduino IDE also went well - after modifying compiler rules to use standard makefiles you can actually use that same IDE to develop and even upload your "sketch" to ZPUino. Unfortunately Arduino developers do not see this "Makefile-based" build as a good thing, let's hope they do reconsider their position - everyone wins if they do.


Monday, October 4, 2010

Bootloader up and running.

Looks like bootloader and programmer work OK. Still a few things to do, like retry transmission, better detection of ZPUino on startup, and implement drivers for flash other than M25P16.

But generic flash programming seems to work very well. In future, if FPGA is also using SPI for program storage we can program both (FPGA and ZPUino) from a single application (will be slower, because I'm limiting programming to 115200 baud).

Jack decided to offer me a prototype of the upcoming Papilio Overshield (It's a Spartan3E with SPI flash and voltage level converters (5v) that looks like another arduino shield). Looks very promising.


Saturday, September 25, 2010

Redesigning bootloader and programmer

Redesigning bootloader and programmer right now. Last one was more a kind of example, and was definitely too specific for my Micron Flash. So the upcoming changes are:
  • Use HDLC-like protocol, protected by CRC16. This should avoid communication errors and does not add that much overhead. In the future, it might aswell be compatible with my SerPro library (full RPC).
  • Remove specifics from bootloader, move them to programmer. Programmer should be able to identify the flash chip, and choose correct operations accordingly. Page sizes and block sizes differ a lot between flash manufacturers, so the only native operations in bootloader should be READ_FAST, READ_STATUS and READ_JEDEC_ID. All other operations can be issued by programmer in a "generic" way.
Other changes include bootloader identification, flash offset (this one hardcoded in bootloader), and others I see fit while I perform implementation and testing.


Friday, September 24, 2010

Saturday, September 18, 2010

Memory... is never enough.

Low-end (or mid-end) FPGA do not include that much Block RAM as one might wish. For example, XC3S250E has 27KB of Block RAM, XC3S500E includes 45KB. Looks like a lot of RAM for a micro, that is for sure, but do not forget that these do not include any kind of FLASH memory for program storage. So you'll end up using most of this RAM to store program code.

Using an external SPI flash ROM is interesting, but its speed does not allow for fast execution. So I decided to write a small, direct-mapped instruction cache (1KB, 32-byte line size). It's meant to be small and interoperate well with at least alzpu core (zpu classic core, since uses a non-pipelined approach suffers from 1-clock cycle delay, might not be acceptable).

Let's see how it goes.

Tuesday, September 14, 2010

Some music ?

I just tested a "test" application which outputs raw 16-bit unsigned data to SigmaDelta (stored in SPI flash). This data was the left-channel of Helloween's "Handful of Pain", clipped to a few seconds.

Then I connected a simple low-pass and DC filter to output, and connected one headphone.

And I heard the music very well :) Next time I'll try with a SD card, flash is too small for raw music.

Output frequency was 44100Hz, like CD. SigmaDelta outputs at 50MHz. That means an oversampling of 1133. Should be enough for any filter to settle down.


ZPUino is born (almost!)

Hello all, and welcome one of my newest projects, ZPUino.

What ZPUino is, you may ask ? Well, is a SoC (System On-a-Chip) comprising one small CPU, a few devices, and it's meant be implemented on a FPGA and mimic, to some extent, the so sucessfull Arduino platform.

I'll keep you posted about general updates and news about the project.

Right now it's on ALPHA state - meaning that it works, it was already implemented on FPGA and proved working, but not yet ready for production.

You can dowload HDL and some code from

Here's a small description for the device I wrote:

1) What is ZPUino ?

ZPUino is a SoC (System-on-a-Chip) based on Zylin's ZPU 32-bit processor core.

2) What is inside ZPUino ?

Harware-wise, ZPUino currently integrates the following devices:

* ZPU small core (slightly modified) [optional medium-core, still on the forge]
* One UART
* One SPI interface
* Two 16-bit timers
* One TSC (Time Stamp Counter)
* 32-bit GPIO interface
* Interrupt Controller
* One SigmaDelta output [NEW!]

UART Specifications:

* 16-bit prescaler.
* 16-byte deep receive FIFO

SPI Specifications:

* Programmable prescaler.
* Configurable CPOL.
* Configurable SRE (Sample on Rising Edge) [NEW!]
* 8-bit transmission mode, 4 byte (32 bit) receive register.

Timers Specifications:

* 10-bit prescaler
* 16-bit wide counter
* Count-up and Count-down mode
* 16-bit Compare register
* Clear on Compare match support
* Interrupt support on Compare Match
* Output compare Register to GPIO pin (allows PWM) [NEW!]

Interrupt controller Specifications:

* Up to 16 interrupt lines
* Ensures safety (does not allow interrupt recursion)
* 16-bit interrupt mask [NEW!]
* Interrupt Enable bit

GPIO Specifications:

* 32-bit wide (one reserved for SPI)
* Bi-directional (tristate) configuration.

IO Configuration:

* Blocking IO [NEW!]

SigmaDelta Configuration:

* One 16-bit channel [NEW!]
* Blocking and non-Blocking support [NEW!]

Software-wise, it supports the following features:

* 4Kb Bootloader, which includes required emulation code for ZPU.
* Bootstraps code from program flash (shadows into FPGA blockram)
* Serial programming of program flash.
* Serial reset (TODO)

3) Where does it run ?

First implementation was done on Spartan3E 500 (-4), on a S3E Starter Kit, with a M25P16 SPI flash ROM and 32Kbytes RAM.
Implemented sizes (approximate): 841 Slices ( 563 FF, 1094 LUT )
Running speed: 100MHz (50Mhz external clock + DCM)

Current implementation still runs at 100MHz.

I'll keep you posted about news here.