Saturday, September 18, 2010

Memory... is never enough.

Low-end (or mid-end) FPGA do not include that much Block RAM as one might wish. For example, XC3S250E has 27KB of Block RAM, XC3S500E includes 45KB. Looks like a lot of RAM for a micro, that is for sure, but do not forget that these do not include any kind of FLASH memory for program storage. So you'll end up using most of this RAM to store program code.

Using an external SPI flash ROM is interesting, but its speed does not allow for fast execution. So I decided to write a small, direct-mapped instruction cache (1KB, 32-byte line size). It's meant to be small and interoperate well with at least alzpu core (zpu classic core, since uses a non-pipelined approach suffers from 1-clock cycle delay, might not be acceptable).

Let's see how it goes.


  1. Nice!
    I think the cache approach is a good way to go, storing program code in flash is a must. Does the ALZPU support stalls on memory access?

    / Carl

  2. Yes, it can be frozen. I have not yet tried ALZPU as ZPUino core, there are a few technical issues to solve: one is ALZPU uses separate datapaths for code and data, also they can be accessed from more than one stage.

    See this diagram for details:

    Other thing that worries me about cache is that since it is direct mapped, there may exist a lot of misses due to access to emulated instructions. I have some ideas to mitigate that, but not yet implemented.