Low-end (or mid-end) FPGA do not include that much Block RAM as one might wish. For example, XC3S250E has 27KB of Block RAM, XC3S500E includes 45KB. Looks like a lot of RAM for a micro, that is for sure, but do not forget that these do not include any kind of FLASH memory for program storage. So you'll end up using most of this RAM to store program code.
Using an external SPI flash ROM is interesting, but its speed does not allow for fast execution. So I decided to write a small, direct-mapped instruction cache (1KB, 32-byte line size). It's meant to be small and interoperate well with at least alzpu core (zpu classic core, since uses a non-pipelined approach suffers from 1-clock cycle delay, might not be acceptable).
Let's see how it goes.