Tuesday, May 24, 2011


ZPUino extreme (the smallest version of it) successfully implemented and tested on FPGA. This core can do 1-cycle operations on many instructions, hence a lot faster than traditional cores. It also features a separate stack/memory, so memory is now mostly free and available for a DMA engine.

It might need a small redesign however, due to slowness of internal Block RAM. Despite timing things went very good. It still needs interrupt support, but should not be very intrusive.


Thursday, May 5, 2011

ZPUino going wishbone

ZPUino is going wishbone, from the CPU core to the IO devices.

This will ease addition of new peripherals, like the ones in opencores.