Redesigning bootloader and programmer

Redesigning bootloader and programmer right now. Last one was more a kind of example, and was definitely too specific for my Micron Flash. So the upcoming changes are:

• Use HDLC-like protocol, protected by CRC16. This should avoid communication errors and does not add that much overhead. In the future, it might aswell be compatible with my SerPro library (full RPC).
• Remove specifics from bootloader, move them to programmer. Programmer should be able to identify the flash chip, and choose correct operations accordingly. Page sizes and block sizes differ a lot between flash manufacturers, so the only native operations in bootloader should be READ_FAST, READ_STATUS and READ_JEDEC_ID. All other operations can be issued by programmer in a "generic" way.

Other changes include bootloader identification, flash offset (this one hardcoded in bootloader), and others I see fit while I perform implementation and testing.

Álvaro

New forum

Jack Gassett, from Gadget Factory, was kind enough to create a Forum on their website.

http://www.gadgetfactory.net/gadgetforum/index.php?board=20.0

Thanks Jack!

Memory... is never enough.

Low-end (or mid-end) FPGA do not include that much Block RAM as one might wish. For example, XC3S250E has 27KB of Block RAM, XC3S500E includes 45KB. Looks like a lot of RAM for a micro, that is for sure, but do not forget that these do not include any kind of FLASH memory for program storage. So you'll end up using most of this RAM to store program code.

Using an external SPI flash ROM is interesting, but its speed does not allow for fast execution. So I decided to write a small, direct-mapped instruction cache (1KB, 32-byte line size). It's meant to be small and interoperate well with at least alzpu core (zpu classic core, since uses a non-pipelined approach suffers from 1-clock cycle delay, might not be acceptable).

Let's see how it goes.

Some music ?

I just tested a "test" application which outputs raw 16-bit unsigned data to SigmaDelta (stored in SPI flash). This data was the left-channel of Helloween's "Handful of Pain", clipped to a few seconds.

Then I connected a simple low-pass and DC filter to output, and connected one headphone.

And I heard the music very well :) Next time I'll try with a SD card, flash is too small for raw music.

Output frequency was 44100Hz, like CD. SigmaDelta outputs at 50MHz. That means an oversampling of 1133. Should be enough for any filter to settle down.

Álvaro

ZPUino is born (almost!)

Hello all, and welcome one of my newest projects, ZPUino.

What ZPUino is, you may ask ? Well, is a SoC (System On-a-Chip) comprising one small CPU, a few devices, and it's meant be implemented on a FPGA and mimic, to some extent, the so sucessfull Arduino platform.

I'll keep you posted about general updates and news about the project.

Right now it's on ALPHA state - meaning that it works, it was already implemented on FPGA and proved working, but not yet ready for production.

You can dowload HDL and some code from http://repo.or.cz/w/zpu/zpuino.git.

Here's a small description for the device I wrote:

1) What is ZPUino ?

ZPUino is a SoC (System-on-a-Chip) based on Zylin's ZPU 32-bit processor core.

2) What is inside ZPUino ?

Harware-wise, ZPUino currently integrates the following devices:

* ZPU small core (slightly modified) [optional medium-core, still on the forge]
* One UART
* One SPI interface
* Two 16-bit timers
* One TSC (Time Stamp Counter)
* 32-bit GPIO interface
* Interrupt Controller
* One SigmaDelta output [NEW!]

UART Specifications:

* 16-bit prescaler.
* 16-byte deep receive FIFO

SPI Specifications:

* Programmable prescaler.
* Configurable CPOL.
* Configurable SRE (Sample on Rising Edge) [NEW!]
* 8-bit transmission mode, 4 byte (32 bit) receive register.

Timers Specifications:

* 10-bit prescaler
* 16-bit wide counter
* Count-up and Count-down mode
* 16-bit Compare register
* Clear on Compare match support
* Interrupt support on Compare Match
* Output compare Register to GPIO pin (allows PWM) [NEW!]

Interrupt controller Specifications:

* Up to 16 interrupt lines
* Ensures safety (does not allow interrupt recursion)
* 16-bit interrupt mask [NEW!]
* Interrupt Enable bit

GPIO Specifications:

* 32-bit wide (one reserved for SPI)
* Bi-directional (tristate) configuration.

IO Configuration:

* Blocking IO [NEW!]

SigmaDelta Configuration:

* One 16-bit channel [NEW!]
* Blocking and non-Blocking support [NEW!]

Software-wise, it supports the following features:

* 4Kb Bootloader, which includes required emulation code for ZPU.
* Bootstraps code from program flash (shadows into FPGA blockram)
* Serial programming of program flash.
* Serial reset (TODO)

3) Where does it run ?

First implementation was done on Spartan3E 500 (-4), on a S3E Starter Kit, with a M25P16 SPI flash ROM and 32Kbytes RAM.
Implemented sizes (approximate): 841 Slices ( 563 FF, 1094 LUT )
Running speed: 100MHz (50Mhz external clock + DCM)

Current implementation still runs at 100MHz.

I'll keep you posted about news here.

Álvaro