hi alvie, i'm interested to test the alpha i have a papilio 500k
one question, will it be possible now to just configure the fpga (in ram) and not to program the flash each time we upload the sketch ? (like how we proceed with the avr8 arduino-like IDE from Jack Gassett for the papilio) i find it annoying to consume a flash cycle each time we want to test one software modification while developping/debugging
Yes, I have finished the Upload to RAM feature. You can use from the commandline using the "-U" flag to programmer, or in IDE (just press CTRL+UPLOAD to do Upload-To-Ram).
I'll prepare the 500K image during the weekend (it's the only one still needing tweaking).
You will need to download the new IDE also, and if you're using Linux the new toolchain (for Windows the toolchain is included in IDE distro).
Do you have an idea of the amount of gates taken by zpuino on a papilio 250k ? I tried to build it myself with ISE, but failed to compile entirely (there are some missing files apparently ?) but the synthesis told me ~80% of slices for a 250k, which is not so much, for a small 250k...
Number of Slice Flip Flops: 2,344 out of 4,896 47% Number of 4 input LUTs: 3,166 out of 4,896 64% Logic Distribution: Number of occupied Slices: 2,220 out of 2,448 90%
Note: I did not yet changed the default upload method, so for Upload-to-RAM you need to press CTRL then the upload button. The message should change to "Upload to memory".
I'm interested to be an alpha tester. What do I need to do to become one? noel [at]makerdude.com
ReplyDeleteWhich board do you have ? I'll prepare some bitfiles and software. Also, which OS do you use ?
ReplyDeletehi alvie,
ReplyDeletei'm interested to test the alpha
i have a papilio 500k
one question, will it be possible now to just configure the fpga (in ram) and not to program the flash each time we upload the sketch ?
(like how we proceed with the avr8 arduino-like IDE from Jack Gassett for the papilio)
i find it annoying to consume a flash cycle each time we want to test one software modification while developping/debugging
Yes, I have finished the Upload to RAM feature. You can use from the commandline using the "-U" flag to programmer, or in IDE (just press CTRL+UPLOAD to do Upload-To-Ram).
ReplyDeleteI'll prepare the 500K image during the weekend (it's the only one still needing tweaking).
You will need to download the new IDE also, and if you're using Linux the new toolchain (for Windows the toolchain is included in IDE distro).
I'll get in touch with you by email.
Great, Alvie !! :-)
ReplyDeleteDo you have an idea of the amount of gates taken by zpuino on a papilio 250k ?
I tried to build it myself with ISE, but failed to compile entirely (there are some missing files apparently ?)
but the synthesis told me ~80% of slices for a 250k, which is not so much, for a small 250k...
For P250:
ReplyDeleteNumber of Slice Flip Flops: 2,344 out of 4,896 47%
Number of 4 input LUTs: 3,166 out of 4,896 64%
Logic Distribution:
Number of occupied Slices: 2,220 out of 2,448 90%
Care to report missing files ?
sure :
ReplyDeleteprom-generic-dp-32.vhd (okay, this i managed to generate with gen-prom-generic-dualport.pl)
zpuino_debug_spartan3e.vhd
papilio_one_top.sch
where can i download the 1.0 alpha IDE ? Maybe with a 500k bitfile also ?
thanks alvie
concerning the slice stats, that's what i imagined
the 250k is nearly full...
(personally i have a 500k, i asked for a friend of mine)
S3E500 bitfile
ReplyDeleteS3E250 bitfile
1.0 IDE
Note: I did not yet changed the default upload method, so for Upload-to-RAM you need to press CTRL then the upload button. The message should change to "Upload to memory".
I'm willing to alpha test. I've got access to a Spartan 3E· Starter Kit (500 k gates). Any chance I could get a bitfile and a Linux 1.0 IDE?
ReplyDeleteSure. I'm planning to release an updated version this week, and I'll include the Linux version too.
ReplyDelete